Glossary

Glossary

The words the Sparsr reference pages use, in one place. Each entry describes the planned architecture. The memory map shows the memories in one table.

The machine

  • Host. The ordinary computer the Sparsr card is plugged into. It runs your application.
  • Card. The Sparsr accelerator, on PCIe.
  • Scalar core. The 32-bit RISC-V (RV32I) processor on the card. It runs a kernel's control flow.
  • Wide datapath. The other half of the processor: 32 wide registers and the wide ALU, which work on a whole row at once.
  • Kernel. The program the host loads into IMEM and runs on the card.
  • Batch. One run of a kernel, from its first instruction until it returns, exits or faults.
  • Wide instruction. One of Sparsr's own instructions, in the RISC-V custom-0 opcode. See Instruction Set Architecture.
  • WL and WS. The wide load and the wide store. They copy one raw row between WMEM and a wide register, by row number.

Rows and lanes

  • Row. One wide register's worth of data: 8,192 bits, or 1,024 bytes.
  • Lane. A 32-bit piece of a row. A row has 256 lanes. The wide ALU never passes a carry from one lane to the next.
  • Wide register. A register that stores one row. There are 32, w0 to w31.
  • Raw row. A row's 1,024 bytes, with no compression.

The memories

  • IMEM (instruction memory). The kernel's code: 64 KiB on the chip, at address 0x0000_0000.
  • DMEM (data memory). The kernel's stack, globals and scalar data: 64 KiB on the chip, at address 0x8000_0000.
  • WMEM (wide memory). The on-chip memory of rows: 4,096 rows. Wide instructions address it by row number, and RV32I loads and stores address its bytes. Rows in WMEM are always raw.
  • WMEM byte window. The part of the scalar address map that shows WMEM's rows as bytes, from 0x9000_0000. Row n starts at 0x9000_0000 + n * 1,024.
  • XMEM (extended memory). The off-chip memory of rows: 16 GiB. Only the DMA and the host read and write it. No instruction addresses it.
  • Tile. A block of rows from a large data set, small enough to fit in WMEM.

Moving rows

  • DMA (direct memory access engine). The engine that copies blocks of rows between XMEM and WMEM while the core keeps running. A kernel and the host start a copy through the same control registers, at 0xFFE0_0000. See WMEM, XMEM and the DMA.
  • Frame. The unit the host and the card exchange over PCIe: 256 words of 32 bits, with 3 header words and 253 payload words. See Host Wire Format.
  • Slot. One row, or one piece of a raw row, inside a frame. Its tag says whether it is raw or LIL, and how long it is. A frame contains up to four.
  • LIL (list of lanes). The compressed form of a sparse row. It lists only the lanes with at least one 1-bit, each with its lane number. A row with more than 102 non-zero lanes is never sent as LIL.
  • Raw escape. The rule that a row too dense for LIL is sent raw. The host never cuts a row short to make it fit.
  • Decoder. The one LIL decoder on the card, on the path into WMEM. It expands a LIL row to a raw row. The card never compresses a row.

Older names

  • CMEM. An older name for the row memory, from "compressed memory". Rows in WMEM are raw, so the name is retired.